1 . Field of the Invention
Embodiments of the present invention generally relate to methods for filling openings in a substrate with metal. Specifically, methods for pre-treating the substrate prior to filling openings are provided.
2 . Description of the Related Art
Reliably producing nanometer-sized features is one of the key technologies for the next generation of semiconductor devices. The shrinking dimensions of circuits and devices have placed increased demands on processing capabilities. The multilevel interconnects that lie at the heart of integrated circuit technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to future success and to the continued effort to increase circuit density and quality of individual substrates. Also, in some processes, openings in a field region of a substrate must be filled with metal to form contacts for a chip package. All such features must be formed substantially without embedded voids or spaces. Voids inhibit the electrical properties of the features, reducing the reliability of the device.
Metallization of openings, such as trenches or holes, formed on substrates has conventionally focused on various plating processes, including electroplating. A substrate having openings to be filled with metal is exposed to an electrolyte solution while a voltage bias is applied. Electrolyte reacts with the biased substrate to deposit metal. FIG. 1 illustrates a substrate in various stages of such an electroplating process. In FIG. 1A, a substrate comprises a first layer 100 and a second layer 102. In FIG. 1B, the second layer 102 is patterned to create openings 104, exposing the first layer 100. If the first layer 100 is conductive, metal may be directly deposited in the openings 104. If both the first and second layers, 100 and 102, respectively, are non-conductive, a conductive layer must be added to facilitate electroplating. FIG. 1C illustrates a substrate with the non-conductive layers 100 and 102, and openings 104. A barrier layer 106 and a conductive seed layer 108 have been formed over the substrate. The barrier layer 106 prevents conductive species from the seed layer 108 from migrating into the non-conductive layers 102 and 104. The conductive seed layer 108 allows electroplating to proceed, as shown in FIG. 1D, where a conductive layer 110 has been formed, overfilling the openings 104. The process is complete with planarization in FIG. 1E to remove excess conductor, seed, and barrier layer, exposing the non-conductive second layer 102.
Currently, copper and copper alloys have become the metals of choice over aluminum for nanometer-sized interconnect technology, as well as for contact formation in chip packaging processes. Copper has a lower electrical resistivity (about 1.7 μΩ-cm compared to about 2.7 μΩ-cm for aluminum), a higher current carrying capacity, and significantly higher electromigration resistance than aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has good thermal conductivity and is available in a highly pure form.
In a typical electroplating process such as that illustrated by FIG. 1, metal is deposited on the field region as well as on the sidewalls and bottoms of the openings. As metal grows on the field and sidewalls, the openings get smaller. Due to characteristics of processes such as PVD sputtering commonly used to form seed layers, a slight overhang generally develops near the tops of the openings. As metal deposition proceeds, overhang from one side of an opening grows to meet overhang from the other side, blocking any further access to the opening by the electrolyte solution. In this way, a void or space forms in the metalized feature. FIG. 2 illustrates a substrate after a typical electrochemical deposition process. Metal layer 202 has been deposited having voids 204 therein. The voids 204 reduce the electrical performance of the resulting contacts.
Moreover, substantial excess metal is used in today's common electroplating processes. The substrate shown in FIG. 2 must be planarized following deposition, and all the excess metal of layer 202 is discarded. In contact formation applications for chip packaging, the openings to be filled may be as large as 100 micrometers (μm) wide. Filling such openings with 100 μm of metal using the standard process nominally requires that 100 μm of metal be deposited on field regions as well, metal which is subsequently discarded.
Thus, there remains a need for a method of filling openings with conductive material in an electroplating process, while limiting deposition on field regions.